The present invention relates to a video format signal generator for producing a composite video format signal to be applied to a CRT display unit. Such a video format signal generator is based on a CRT controller, together with control means (such as a CPU) data memory means, video memory means etc, whose functions may be provided by a personal computer for example. Such a video format signal generator can in general be controlled to selectively operate in an externally synchronized mode and an internally synchronized mode. In the externally synchronized mode, a composite video signal supplied from some external source (this being referred to in the following simply as an external video signal) is input to a sync separator circuit whereby vertical and horizontal sync pulse signals (referred to in the following simply as V and H sync signals) are derived from the external video signal. These V and H sync signals are applied to the CRT controller, to respectively reset a horizontal counter circuit and a vertical counter circuit, which control the timing relationships of components of the composite video format signal from the CRT controller. More specifically, the counter period of the vertical counter circuit controlled by the V sync signal in this way determines the vertcial scanning period of the output video signal from the CRT controller, while the count period of the horizontal counter circuit, controlled by the H sync signal, serves to determine the horizontal scanning period of the output video signal. The counting operations of these counter circuits are controlled by a clock signal of fixed frequency. Generally speaking, the period of this clock signal corresponds to the width of a picture element of the CRT display, i.e. the width of the minimum size of dot element which can be displayed. In the prior art, this clock signal for operation of the horizontal counter circuit is generated independently of the H sync signal derived from the external video signal, i.e. the clock signal is not synchronized with this clock signal. As a result, if for example a vertical line comprising a set of vertically stacked dot elements is displayed on the CRT, the lack of synchronization between the clock signal controlling the horizontal counter circuit in the CRT controller and the H sync signal (which determines the horizontal scanning period) will result in a successively staggered condition of the vertically stacked dots on the display, resulting in a type of fringed effect appearing on vertical lines. This is a very undesirable effect, which is unavoidable with prior art types of video format signal generator having a relatively simple circuit configuration.
There is therefore a requirement for circuit means, preferably simple and economical to implement, whereby the clock signal described above can be accurately synchronized with the H sync signal derived from an external video signal, to eliminate the objectionable display effect described above.